The present invention generally relates to semiconductor devices and more particularly to a contact structure of a semiconductor device for use in miniaturized semiconductor devices such as submicron devices, as well as a semiconductor device that uses such a contact structure. Further, the present invention relates to a contact structure for use in semiconductor integrated circuits having a multilayer interconnection structure and a semiconductor integrated circuit having such a contact structure.
With the development of photolithography, miniaturization of semiconductor devices is continuing. Currently, semiconductor devices having a submicron pattern size are produced successfully by using an advanced photolithographic system. Further, recent semiconductor integrated circuits of a large integration density and hence including large number of semiconductor devices therein, are increasingly using a multilayer interconnection structure in which wiring or interconnection patterns are provided in plural layers with an interlayer insulation structure intervening therebetween.
When producing such submicron semiconductor devices in the form of integrated circuit, it is necessary to provide minute contact holes of submicron size on an insulation layer having a stepped surface.
FIGS. 1A and 1B show a typical example of forming such a minute contact hole in an insulation layer having a stepped surface.
Referring to FIG. 1A showing a part of a semiconductor integrated circuit, it will be noted that a field oxide film 2 is provided on a semiconductor substrate 1 so as to define an active region that includes a diffusion region 3. On the field oxide film 2, it will be noted that a conductor pattern 4 having a submicron width is provided, wherein the conductor pattern 4 may be a gate pattern of a MOS transistor. In this case, the conductor pattern 4 extends in the direction generally perpendicularly to the sheet of the drawing and forms a gate electrode in an active region not illustrated in FIG. 1A.
The conductor pattern 4 is covered by an insulation film 5 that may include a silicon oxide film deposited on the substrate 1 by a CVD process so as to cover the diffusion region 3 as well as the field oxide film 2 including the conductor pattern, wherein a planarization layer of BPSG or the like, may be provided further on the silicon oxide film to form the foregoing insulation film 5.
In the state of FIG. 1A, a photoresist 6 is applied on the insulation film 5, wherein the photoresist 6 includes openings 6A and 6B formed by a photolithographic process that includes exposure and development of the photoresist 6, such that the surface of the insulation film 5 is exposed at the openings 6A and 6B.
Next, in the step of FIG. 1B, a reactive ion etching process is applied to the structure of FIG. 1A while using the photoresist 6 as a mask, to form contact holes 5A and 5B respectively in correspondence to the openings 6A and 6B of FIG. 1A. The contact holes 5A and 5B thus formed expose the diffusion region 3 and the conductor pattern 4 respectively, and the structure of FIG. 1B is ready for formation of a wiring pattern thereon for interconnecting various parts of the semiconductor devices formed on the substrate 1.
In such a process, it should be noted that, because of the existence of stepped structure on the part of the insulation layer 5 covering the conductor pattern 4, which in turn is located on the field oxide film 2, there is a tendency that the photoresist 6 has a reduced thickness t.sub.2 in the region immediately above the conductor pattern 4 where the opening 6B is formed, as compared with a thickness t.sub.1 for the part of the photoresist 6 located above the diffusion region 3 on which the opening 6A is formed. Further, associated with the reduced thickness of the photoresist 6 on the part located above the conductor pattern 4, the insulation film 5 also has a reduced thickness in the part covering the conductor pattern 4 as compared with the part covering the diffusion region 3. Such a variation in the thickness of the insulation film 5 may reach as much as twice the minimum thickness of the film 5.
In such a case, the etching of the layer 5 immediately reaches the conductor pattern in the opening 6B while in the state that the etching of the layer 5 is still in progress in the opening 6A. In such a case, chemical species produced as a result of interaction between the plasma used in the reactive ion etching process and the conductor pattern 4, attack the side wall of the contact hole 5B, and the size of the contact hole 5B is substantially increased as a result as compared with a nominal size indicated in FIG. 1B by a broken line. Further, the opening 6B of the resist 6 may increase the size thereof as indicated in FIG. 1A by arrows as a result of continuous application of plasma to the photoresist 6 in correspondence to the part where the thickness of the resist 6 is reduced. It should be noted that, while the photoresist 6 has a large resistance against etching as compared with the insulation film 5, such a resistance is by no means infinite.
As a result, the conventional process and the contact structure produced as a result of such a process have suffered from the problem of uncontrolled increase in the size of the contact hole, known as CD (critical dimension) loss. Further, such a contact hole that experienced the problem of CD loss generally shows an irregular shape as indicated in FIG. 2. It should be noted that such an irregular shape occurs as a result of attack of the contact hole side wall by the species produced as a result of reaction between the plasma and the conductor such as the conductor pattern 4.
When an electric contact is formed at such an irregular contact hole, there tends to occur the problem of electromigration in which the electrons concentrated to sharp points in the contact hole induce a displacement of the metal atoms filling the contact hole, leaving behind a void. Similarly, there occurs the problem of stress migration. Thereby, the electrical contact becomes unreliable and the life-time of the contact is reduced significantly.
Further, such an unwanted and uncontrolled increase in the size of the contact hole can be detrimental to minute semiconductor devices such as submicron devices in which the conductor pattern 4 has a width smaller than one micron.
In addition, the existence of stepped structure on the surface of a layer in which a submicron contact hole is to be formed, raises the well known problem of insufficient focal depth of the optical system that is used in a high resolution photolithography. It should be noted that the high resolution optical exposure systems for use in high-resolution, submicron photolithography generally have an optical system of large numerical aperture for increased resolution, while the optical system of such a large numerical aperture can provide only a very limited focal depth. Thus, simultaneous exposure of contact holes at two different levels is extremely difficult as long as such a high resolution optical exposure system is used.
In relation to the formation of minute, submicron contact holes, various proposals are made so far.
For example, the Japanese Laid-open Patent Publication 4-125925 describes a process in which a minute contact hole is formed in a larger, but shallower depression formed in an insulation film.
FIGS. 3A-3E show the process proposed in the foregoing reference.
Referring to FIG. 3, a photoresist 12 is provided on an insulation film 11 covering the surface of a Si substrate 10 in the step of FIG. 3A, wherein the photoresist 12 is formed with an opening 12A as a result of a photolithographic patterning process. The insulation film 11 may include a CVD-deposited silicon oxide film and a PSG layer formed thereon.
Next, in a step of FIG. 3B, an RIE process is applied to the insulation film 11 while using the photoresist 12 as a mask, to form a depression 11A in the insulation film 11 in correspondence to the opening 12A, such that the depression 11A does not reach the substrate 10.
Further, a step of FIG. 3C is conducted in which the process condition of the RIE process is changed such that a deposition occurs rather than etching. As a result, an organic layer 13 of fluorocarbon is deposited on the structure of FIG. 3B as indicated in FIG. 3C.
Next, in a step of FIG. 3D, the process condition is again set such that a reactive ion etching occurs, and the insulation film 11 is etched vertically while using the resist 12 as well as a part of the layer 13 covering the inner wall of the depression 11A as a ask. As a result, a contact hole 11B of a reduced diameter is formed generally at the center of the depression 11A. Further, a part of the organic layer 13 remains as an organic cover 13A that covers the side wall of the depression 11A.
After the step of FIG. 3D, the photoresist 12 as well as the organic cover 13A are removed by an ashing process to form a structure shown in FIG. 3E in which the through hole 11B of a smaller diameter is formed generally at the center of the depression of 11A of a larger diameter.
By forming the contact hole as indicated in FIG. 3E, it is possible to fill the contact hole by a conductive material such as metal relatively easily, even when the contact hole 11B is very small. Thereby, an excellent step coverage is quaranteed.
On the other hand, the device of the foregoing reference has an obvious drawback in that the step formed at the boundary between the contact hole 11B and the depression 11A invites a sudden concentration of electron current in the conductive material filling the contact hole when the electron current flows into the contact hole 11B from the depression 11A. See FIG. 4A that shows the electron current by arrows. It should be noted that such a sudden increase of the current density is particularly harmful to the contact due to the electromigration effect.
The contact structure of FIG. 3E has another serious drawback in that the contact structure has a larger diameter at the top part thereof in correspondence to the depression 11A for contact with an upper interconnection pattern. In such a structure where the top part of the contact structure has an increased diameter, it should be noted that a small alignment error in the contact structure as indicated in FIG. 4B by an arrow may cause an unwanted contact of the conductor material filling the contact structure with an adjacent conductor pattern 14 provided on the insulation film 11.
The Japanese Laid-open Patent Publication 4-206819 describes a formation of a contact structure in which a silicon oxide film is initially etched in a dry etching apparatus with a condition of generally isotropic etching in which etching occurs both in the direction perpendicular to the major surface of the silicon oxide film and in the direction parallel to the major surface of the silicon oxide film, followed by an anisotropic etching process proceeding perpendicularly to the major surface of the silicon oxide film. The same resist mask is used for the isotropic etching phase and the anisotropic etching phase.
The resultant contact structure is somewhat similar to the contact structure of FIGS. 4A and 4B except that the depression 11A is defined by a gently curved surface characteristic to the isotropic etching process. Thus, while the contact structure of the foregoing reference may be free from the problem of sudden increase of the current density explained with reference to FIG. 4A, the contact structure still has the problem of alignment error explained with reference to FIG. 4B,
Further, associated with the use of the resist mask both in the isotropic etching phase and in the anisotropic etching phase, the contact structure suffers from the problem of CD loss caused by the etching of the resist mask, which is by no means ignorable when forming a submicron contact hole.
Further, the Japanese Laid-open Patent Publication 4-206819 describes a method for patterning an Al layer by alternately and repeatedly conducting an RIE process and an oxidation process such that the side wall of the patterned groove is protected by an aluminum oxide film. Such a process, while capable of controlling the cross section of the groove with high precision, has a drawback in that the aluminum oxide layer covering the side wall of the groove act as an etching mask when applying an RIE process to the bottom part of the groove. Thereby, the width of the groove formed at the bottom part of the existing groove becomes inevitably smaller by the amount corresponding to the thickness of the aluminum oxide film covering the side wall of the grooves. Thereby, the groove formed by repeating the RIE and oxidation inevitably has a cross section defined by inclined side walls.
When such a process is applied to a contact hole, the contact hole is inevitably defined by an inclined side wall covered by an oxide, and the contact hole has an increased diameter at the top part thereof as compared with the bottom part. Again, it will be noted that such a tapered contact hole structure is disadvantageous for submicron devices in view of the problems associated with the alignment error explained with reference to FIG. 4B.
Further, the Japanese Laid-open Patent Publication 63-260051 describes a process for forming a contact structure in an insulation film, including the steps of forming a contact hole in the insulation film, covering the side wall of the contact hole by a metal, and filling the contact hole thus covered by the metal by another metal to form a conductive plug. Thereby, formation of void between the conductive plug and the side wall of the contact hole is successfully eliminated, and a reliable electrical contact is guaranteed.
However, the process of the foregoing reference has a drawback that it cannot eliminate the problem of CD loss, as the contact hole itself is formed by using an ordinary resist pattern.
Summarizing above, none of the conventional processes for forming contact holes and the contact structures formed by such processes can provide a solution to the problem of CD loss explained with reference to FIGS. 1A and 1B, particularly in the presence of stepped structure as in the case of recent integrated circuits that generally have a multi-layer interconnection structure.